1. Field of the Invention
This invention relates to data communications in a computer system, and more specifically, to a memory translator hub designed to provide a memory bus from a memory channel.
2. Background Information
Computer systems rely heavily upon Dynamic Random Access Memories (“DRAMs”) to implement system memories due to their simplicity, affordability and memory density. However, it is increasingly difficult to design memory systems that satisfy the size and performance requirements for modern computer systems using DRAMs connected by conventional bus architectures. To overcome these limitations, a memory subsystem can be constructed using a memory channel architecture. Intelligent memory devices are connected by a narrow, high-speed bus, termed a channel. Packets of information are transmitted on the memory channel to communicate between the memory controller and the memory devices. Direct Rambus™ architecture using Rambus® channels is an example of a memory subsystem using a memory channel architecture.
As a new technology, the cost of components, such as Rambus DRAM (RDRAM™), for memory channel subsystems is high and supplies are uncertain. Memory channel devices require a completely different memory interface from conventional memory devices. Memory channel devices are not compatible with previous memory controllers which support more conventional memory components such as Synchronous DRAM (SDRAM) components using a memory bus.
During the transition to computer systems using memory channel subsystems, it would be desirable to build computer systems that can use either a conventional memory bus subsystem or a memory channel subsystem. Memory controllers that can support two or more conventional memory technologies on a single memory bus are known. For example, U.S. Pat. No. 5,893,136, assigned to Intel Corporation, describes a memory controller for independently supporting synchronous and asynchronous DRAM memories. It is possible to support multiple conventional memory technologies with a single memory controller because the memories use a memory bus with the same electrical signaling levels and similar signaling arrangements.
Memory channel architectures use different electrical signaling levels and a novel signaling arrangement. This precludes control of conventional SDRAM memory subsystems with memory channel controllers. Accordingly, there is a need for a memory translator that allows a memory bus subsystem to be connected to a memory channel controller.